september 2012 FDMS8090 powertrench ? power stage ?2012 fairchild semiconductor corporation 1 www.fairchildsemi.com FDMS8090 rev.c bottom top g1 s1 s1 s1 d1 d2 g2 s2 s2 s2 g2 s2 s2 s2 g1 s1 s1 s1 pin 1 pin 1 1 2 3 4 8 7 6 5 contact to d1 (backside) q1 q2 contact to d2 (backside) power 56 FDMS8090 powertrench ? power stage 100 v symmetric dual n-channel mosfet features ? max r ds(on) = 13 m at v gs = 10 v, i d = 10 a ? max r ds(on) = 20 m at v gs = 6 v, i d = 8 a ? low inductance packaging shortens rise/fall times, resulting in lower switching losses ? mosfet integration enables optimum layout for lower circuit inductance and reduced switch node ringing ? 100% uil tested ? rohs compliant general description this device includes two fast sw itching (qgd minimized) 100v n-channel mosfets in a dual power 56 (5 mm x 6 mm mlp) package. the package is enhanced for exceptional thermal performance. applications ? bridge topologies ? synchronous rectifier pair ? motor drives mosfet maximum ratings t a = 25 c unless otherwise noted thermal characteristics package marking and ordering information symbol parameter ratings units v ds drain to source voltage 100 v v gs gate to source voltage 20 v i d drain current -continuous t c = 25 c 40 a -continuous t a = 25 c (note 1a) 10 -pulsed (note 4) 120 e as single pulse avalanche energy (note 3) 253 mj p d power dissipation t c = 25 c 59 w power dissipation t a = 25 c (note 1a) 2.2 t j , t stg operating and storage junction temperature range -55 to +150 c r jc thermal resistance, junction to case 2.1 c/w r ja thermal resistance, junction to ambient (note 1a) 55 device marking device package reel size tape width quantity FDMS8090 FDMS8090 power 56 13 ?? 12 mm 3000 units
FDMS8090 powertrench ? power stage ?2012 fairchild semiconductor corporation 2 www.fairchildsemi.com FDMS8090 rev.c electrical characteristics t j = 25 c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diode characteristics symbol parameter test conditions min typ max units bv dss drain to source breakdown voltage i d = 250 a, v gs = 0 v100 v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 c 70 mv/c i dss zero gate voltage drain current v ds = 80 v, v gs = 0 v1 a i gss gate to source leakage current v gs = 20 v, v ds = 0 v 100 na v gs(th) gate to source threshold voltage v gs = v ds , i d = 250 a 2.0 3.0 4.0 v v gs(th) t j gate to source threshold voltage temperature coefficient i d = 250 a, referenced to 25 c -10 mv/c r ds(on) static drain to source on resistance v gs = 10 v, i d = 10 a 1113 m v gs = 6 v, i d = 8 a1520 v gs = 10 v, i d = 10 a, t j = 125 c 18 20 g fs forward transconductance v ds = 10 v, i d = 10 a24s c iss input capacitance v ds = 50 v, v gs = 0 v, f = 1 mhz 1285 1800 pf c oss output capacitance 301 400 pf c rss reverse transfer capacitance 16 28 pf r g gate resistance 0.1 1.7 3.5 t d(on) turn-on delay time v dd = 50 v, i d = 10 a, v gs = 10 v, r gen = 6 10.6 21 ns t r rise time 4.6 10 ns t d(off) turn-off delay time 17.4 31 ns t f fall time 410ns q g total gate charge v gs = 0 v to 10 v v dd = 50 v, i d = 10 a 19 27 nc q g total gate charge v gs = 0 v to 5 v1015nc q gs gate to source charge 6.1 nc q gd gate to drain ?miller? charge 4.1 nc v sd source-drain diode forward voltage v gs = 0 v, i s = 2 a (note 2) 0.7 1.2 v v gs = 0 v, i s = 10 a (note 2) 0.8 1.3 t rr reverse recovery time i f = 10 a, di/dt = 100 a/ s 49 78 ns q rr reverse recovery charge 54 86 nc notes : 1. r ja is determined with the device mounted on a 1 in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. 3. e as of 253 mj is based on starting t j = 25 c; n-ch: l = 3 mh, i as = 13 a, v dd = 100 v, v gs = 10 v. 100% test at l = 0.3 mh, i as = 29 a. 4. pulsed id limited by junction temperature,td<=10us. please refer to soa curve for more details. a. 55 c/w when mounted on a 1 in 2 pad of 2 oz copper. b. 138 c/w when mounted on a minimum pad of 2 oz copper. g df ds sf ss g df ds sf ss
FDMS8090 powertrench ? power stage ?2012 fairchild semiconductor corporation 3 www.fairchildsemi.com FDMS8090 rev.c typical characteristics t j = 25 c unless otherwise noted figure 1. 012345 0 20 40 60 80 100 120 v gs = 6 v v gs = 5.5 v v gs = 7 v pulse duration = 80 p s duty cycle = 0.5% max v gs = 5 v v gs = 10 v i d , drain current (a) v ds , drain to source voltage (v) on region characteristics figure 2. 0 20 40 60 80 100 120 0.0 0.9 1.8 2.7 3.6 4.5 v gs = 7 v pulse duration = 80 p s duty cycle = 0.5% max normalized drain to source on-resistance i d , drain current (a) v gs = 6 v v gs = 5.5 v v gs = 10 v v gs = 5 v n o r m a l i z e d o n - r e s i s t a n c e vs drain current and gate voltage f i g u r e 3 . n o r m a l i z e d o n r e s i s t a n c e -75 -50 -25 0 25 50 75 100 125 150 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 i d = 10 a v gs = 10 v normalized drain to source on-resistance t j , junction temperature ( o c ) vs junction temperature figure 4. 45678910 0 10 20 30 40 50 60 t j = 125 o c i d = 10 a t j = 25 o c v gs , gate to source voltage (v) r ds(on) , drain to source on-resistance ( m : ) pulse duration = 80 p s duty cycle = 0.5% max o n - r e s i s t a n c e v s g a t e t o source voltage figure 5. transfer characteristics 24681 0 0 20 40 60 80 100 120 t j = 150 o c v ds = 5 v pulse duration = 80 p s duty cycle = 0.5% max t j = -55 o c t j = 25 o c i d , drain current (a) v gs , gate to source voltage (v) figure 6. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 0.001 0.01 0.1 1 10 100 200 t j = -55 o c t j = 25 o c t j = 150 o c v gs = 0 v i s , reverse drain current (a) v sd , body diode forward voltage (v) s o u r c e t o d r a i n d i o d e forward voltage vs source current
FDMS8090 powertrench ? power stage ?2012 fairchild semiconductor corporation 4 www.fairchildsemi.com FDMS8090 rev.c figure 7. 0 4 8 121620 0 2 4 6 8 10 i d = 10 a v dd = 75 v v dd = 25 v v gs , gate to source voltage (v) q g , gate charge (nc) v dd = 50 v gate charge characteristics figure 8. 0.1 1 10 100 1 10 100 1000 10000 f = 1 mhz v gs = 0 v capacitance (pf) v ds , drain to source voltage (v) c rss c oss c iss c a p a c i t a n c e v s d r a i n to source voltage figure 9. 0.01 0.1 1 10 100 1 10 100 t j = 125 o c t j = 25 o c t j = 100 o c t av , time in avalanche (ms) i as , avalanche current (a) u n c l a m p e d i n d u c t i v e switching capability figure 10. 25 50 75 100 125 150 0 12 24 36 48 60 v gs = 6 v limited by package r t jc = 2.1 o c/w v gs = 10 v i d , drain current (a) t c , case temperature ( o c ) m a x i m u m c o n t i n u o u s d r a i n current vs case temperature f i g u r e 1 1 . f o r w a r d b i a s s a f e op erating area 0.01 0.1 1 10 100 500 0.001 0.01 0.1 1 10 100 200 curve bent to measured data 100 us 1 ms 100 ms dc 10 s 1 s 10 ms i d , drain current (a) v ds , drain to source voltage (v) this area is limited by r ds(on) single pulse t j = max rated r t ja = 138 o c/w t a = 25 o c figure 12. 10 -4 10 -3 10 -2 10 -1 110 100 1000 0.1 1 10 100 1000 10000 single pulse r t ja = 138 o c/w t a = 25 o c p ( pk ) , peak transient power (w) t, pulse width (sec) s i n g l e p u l s e m a x i m u m power dissipation typical characteristics t j = 25 c unless otherwise noted
FDMS8090 powertrench ? power stage ?2012 fairchild semiconductor corporation 5 www.fairchildsemi.com FDMS8090 rev.c figure 13. junction-to-ambient transient thermal response curve 10 -4 10 -3 10 -2 10 -1 11 0 100 1000 0.0001 0.001 0.01 0.1 1 2 single pulse r t ja = 138 o c/w duty cycle-descending order normalized thermal impedance, z t ja t, rectangular pulse duration (sec) d = 0.5 0.2 0.1 0.05 0.02 0.01 p dm t 1 t 2 notes: duty factor: d = t 1 /t 2 peak t j = p dm x z t ja x r t ja + t a typical characteristics t j = 25 c unless otherwise noted
FDMS8090 powertrench ? power stage ?2012 fairchild semiconductor corporation 6 www.fairchildsemi.com FDMS8090 rev.c dimensional outline and pad layout
FDMS8090 powertrench ? power stage ?2012 fairchild semiconductor corporation 7 www.fairchildsemi.com FDMS8090 rev.c trademarks the following includes registered and unregistered trademarks an d service marks, owned by fairchild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes with out further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of th e application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s wo rldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized fo r use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used here in: 1. life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms 2cool? 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